PARLAK: Parametrized Lock Cache Synthesizer

An effective and scalable synchronization mechanism is necessary for a heterogeneous multiprocessor shared-memory system-on-a-chip (SoC). A system-on-a-chip lock cache (SoCLC) is a simple hardware unit that can easily be integrated to an SoC as an intellectual property (IP) core via the system bus and has been shown to achieve speedups of 55% and 27% in realistic examples at a very small (13,000 gates) hardware cost. In this paper, we present PARLAK, a parametrized lock cache synthesizer tool. PARLAK generates a synthesizable SoCLC architecture with a user specified number of lock variables and user specified number and type(s) of processor(s). Several configurations of SoCLC hardware have been generated using PARLAK and the designs have been synthesized in Design Compiler from Synopsys. For example, PARLAK can generate a full range of customized SoCLCs, from a version for two processors with 32 lock variables occupying 1,790 gates of area to a version for 14 processors with 256 lock variables occupying 37,380 gates of area (in TSMC 0.25µ technology). The synthesis area results reported in this paper indicate that the area occupied by SoCLC increases linearly as the number of locks/processors is increased. PARLAK is an important contribution to IP-generator tools for both custom SoC design and programming of reconfigurable SoC designs.